Topological Layout Design of Submicron CMOS Integrated Circuits

Student: Dudnikov Kirill

Faculty: HSE Tikhonov Moscow Institute of Electronics and Mathematics (MIEM HSE)

Educational Programme: Infocommunication Technologies and Systems (Bachelor)

Final Grade: 7

Year of Graduation: 2017

The main purpose of this work is to design the topology of the 8-bit shift register with linear feedbacks using submicron CMOS technology with design standards of 0.25 μm. The object of research in the work is submicron CMOS circuits and technologies, the norms of topological design. In the first chapter of the work, theoretical aspects of designing CMOS digital submicron circuits are considered. The second chapter describes the process of developing the topology of the selected circuit. The result of the work is the drawn topology drawings for individual cells and the total adder circuit. Verification of the full circuit of the adder for compliance with design rules was also carried out, which resulted in correction of design errors, as a result of which the circuit became fully compliant with the set standards.

Full text (added May 30, 2017)

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