Development of a Network-on-chip HDL Model

Network-on-Chip (NoC) are a new milestone in the development of microprocessor systems, as they allow to increase a number of computing cores and additional modules in System-on-Chip (SoC). Therefore, tools are required for their prototyping and simulation. The paper presents the implementation of a generated NoC with various parameters in the Verilog language, which supports mesh topology, torus and circulant with 2 generatrices topologies. The parameters of the model that can be configured are the number of nodes, the size of the router's buffer, the parameters of transmitted packets, the frequency of their generation, specific parameters for each topology, and network traffic settings. A simple router, their communication system, and additional programs for working with the model have been developed. The paper consists of 38 pages, 17 sources, 21 figures, 6 tables used.