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Simulation of Temperature Influence on CMOS Logical Circuits Tolerance to Single Events

Student: Borisov Dmitrii

Supervisor: Igor A. Kharitonov

Faculty: HSE Tikhonov Moscow Institute of Electronics and Mathematics (MIEM HSE)

Educational Programme: Electronic Engineering (Master)

Final Grade: 8

Year of Graduation: 2019

Logic semiconductor circuits, which are used in the aircraft industry or in the space industry, are exposed by heavy charged particles and temperature. The combination of these effects can lead to a single event upset (SEU) in work. In this research work, the interrelation of these effects is studied, and the stability of logical CMOS circuits to their joint effects is also studied. In this diploma paper modeled the impact of heavy particles on CMOS memory cells at different temperatures for manufacturing techniques: 130 nm, 90 nm and 65 nm. The simulation was performed using the mixed TCAD-SPICE simulation method. Calculated loss of signals from memory cells based on simulation results. According to the results of the study, conclusions were drawn from the obtained results of the research work.

Full text (added May 19, 2019)

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