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Regular version of the site

Computer Architecture

2019/2020
Academic Year
ENG
Instruction in English
3
ECTS credits
Course type:
Elective course
When:
1 year, 3 module

Instructor

Course Syllabus

Abstract

Computer architecture is a specification detailing how a set of software and hardware technology standards interact to form a computer system or platform. In short, computer architecture refers to how a computer system is designed and what technologies it is compatible with.
Learning Objectives

Learning Objectives

  • give students an idea of the principles of computer architecture
  • inculcate in students the skills of research work, which implies an independent study of the working documentation, specific tools and software tools that allow simulating the operation of a computer.
Expected Learning Outcomes

Expected Learning Outcomes

  • • understand the evolution of the distributed computing from its early beginnings as multi-processor and multi-computer systems, to computer networks, to the emerging cloud, edge (fog, dew) and heterogeneous computing environments;
  • • understand the existing distributed computing paradigms and systematic issues;
  • • understand application areas of distributed computing technology, such as scientific computing, big data, machine learning, data mining and virtual worlds;
  • • be familiar with existing computing techniques, technologies and tools;
  • • have built a distributed computing application system using available technologies and/or tools; understand evaluation techniques for successful design and development of efficient and effective application systems.
Course Contents

Course Contents

  • Introduction, Instruction Set Architecture, and Microcode.
  • Pipelining Review.
  • Cache Review
  • Superscalar 1
  • Superscalar 2 & Exceptions
  • Superscalar 3
  • Superscalar 4
  • VLIW 1
  • VLIW2
  • Branch Prediction
  • Advanced Caches 1
  • Advanced Caches 2
  • Memory Protection
  • Vector Processors and GPUs
  • Multithreading
  • Parallel Programming 1
  • Parallel Programming 2
  • Small Multiprocessors
  • Multiprocessor Interconnect 1
  • Multiprocessor Interconnect 2
  • Large Multiprocessors (Directory Protocols)
Assessment Elements

Assessment Elements

  • Partially blocks (final) grade/grade calculation Exam
  • non-blocking Conversation with the teacher
Interim Assessment

Interim Assessment

  • Interim assessment (3 module)
    0.3 * Conversation with the teacher + 0.7 * Exam
Bibliography

Bibliography

Recommended Core Bibliography

  • Архитектура компьютера, Таненбаум Э., Гороховского Ю., 2011
  • Архитектура компьютера, Таненбаум Э., Остин Т., 2014

Recommended Additional Bibliography

  • - Калачев А.В. — Многоядерные процессоры - Национальный Открытый Университет "ИНТУИТ" - 2016 - ISBN: 78-5-9963-0349-6 - Текст электронный // ЭБС Лань - URL: https://e.lanbook.com/book/100654