The objective of this study is to increase the throughput and reduce hardware costs in Networks-on-chip (NoCs) by developing NoC models of different levels of abstraction to develop a topological approach to NoC design based on circulant topologies and further developing methods and tools for their synthesis and modeling.
Although the idea of using circulant topologies as the basis of NoCs was not considered in works on this problem, our preliminary analysis of the characteristics of the known circulant topologies suggests that they have better characteristics than the most common regular mesh and torus topologies. The works by E.A. Monakhova note the complexity of the problem of synthesis of circulants for a large number of nodes, but it was partially solved at the previous stage of the study by developing software for the synthesis of circulant topologies which made it possible to obtain the necessary topologies with a number of nodes sufficient for NoC implementation. Some of the most promising classes of circulants for use in NoCs were also identified, and a number of routing algorithms in them were developed. As part of the work, software for the synthesis of circulant topologies was improved, new routing algorithms in NoCs based on circulant topologies were developed, and existing models of various levels of abstraction were created and adapted for modeling and synthesis of NoCs based on circulant topologies for which modern mathematical analysis methods, as well as methods of parallelization of calculations, etc. were used.
Empirical basis of the study
This project is a continuation of previous studies: from 2009 to the present, various basic NoC topology synthesis techniques have been developed and implemented programmatically, NoC routing algorithms with new topologies have been developed, and a complex of modules and components for the synthesis of multiprocessor NoCs based on soft processor cores has been presented and NoC models of different levels of abstraction.
In 2018, tools for the synthesis of various circulant topologies were developed, several classes of circulants were synthesized, routing algorithms in NoCs based on these topologies were proposed, and the first steps were taken to develop a synthesis of NoC HDL implementations (based on the schoolMIPS own processor core and NoCSimp router) to evaluate hardware costs for the implementation of such topologies.
As part of this work, in 2019, previously begun studies were continued: the topology synthesis algorithm was improved to increase its speed, new and improved existing routing algorithms for various circulant families were developed, new and modified existing NoC models of different levels of abstraction were developed and tested Infrastructure for creating hybrid models for NoC design was prepared.
Results of work
As part of a scientific project, circulant topologies and routing algorithms in them were considered as the basis for building NoC communication subsystems.
The algorithm was improved, and the software package for the synthesis of circulants with desired characteristics was developed. The applied methods of search acceleration, parallelization of calculations, etc. made it possible to accelerate the synthesis of circulants by several orders in comparison with the basic algorithm and to obtain families of optimal circulants of different dimensions with the number of nodes reaching thousands.
It was proposed to use circulants of type С (N; D, D + 1) as optimal two-dimensional circulants, and a routing algorithm in them was developed. It was experimentally shown that such circulants can increase throughput and reduce hardware costs for implementing NoCs with two-dimensional circulant topology.
A number of different high-level models in various programming languages in order to provide support for circulant topologies were modified, and the conducted experiments showed the adequacy of such models and their effectiveness for various applications.
An HDL model providing support for NoC modeling with circulant topologies was developed. Due to the use of HDL, high modeling accuracy was ensured, and to increase the speed of the model, parallel execution of several processes was ensured, and auxiliary scripts that allow finding critical points of NoC bandwidth limit by reducing the number of simulation cycles were have been developed. The HDL model can be synthesized in the RTL representation which allows it to be used for event simulation at the circuit level, as well as for NoC prototyping. The results of model testing confirmed its adequacy.
The infrastructure for the development of a hybrid model to combine several models of different levels of abstraction was fully prepared. The entire NoC design cycle (from the initial quick evaluation of NoC simulation to select its characteristics up to the RTL simulation and FPGA prototyping) will be provided.
The degree of implementation, recommendations for implementation or the results of R&D implementation
Results: new families of circulant topologies with the number of nodes reaching thousands; new routing algorithms in circulant topologies; new models of different levels of abstraction for NoC modeling which support circulant topologies; NoC simulation results with various topologies.
In the framework of R&D, 3 certificates for computer programs were collected.
The results of a scientific project can be the basis for the development of a hybrid model to combine several models of different levels of abstraction. The hybrid model will provide the entire NoC design cycle: from the initial quick evaluation of NoC simulation to select its characteristics up to the RTL simulation and FPGA prototyping.