Study of Networks-on-Chip with Various Types of Topologies Using Garnet 2.0 Simulator

Student: Zaytsev Semen

Faculty: HSE Tikhonov Moscow Institute of Electronics and Mathematics (MIEM HSE)

Educational Programme: Computer Systems and Networks (Master)

Year of Graduation: 2020

This paper is devoted to the study of networks on a chip in the simulator Garnet 2.0. In the first chapter of the paper, the concept of networks on a chip is described. The second chapter reviews the simulators of networks on a chip and selects a simulator for further research. The main part of the study is the operation of networks on a chip with respect to given parameters. To conduct the study, scripts were developed to quickly launch the simulator and obtain results after it. The study revealed the advantages and disadvantages of various configurations of launching networks on a chip, which include topology, a pattern for implementing network traffic, and a routing algorithm.

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